1. Field of the Invention
The present invention relates to an address exclusive control system and an address exclusive control method which enable a precise exclusive control related to a next request by retaining not only an address but also the type of a request and the destination of access in a register.
2. Description of the Related Art
FIG. 1 is a block diagram showing an outline configuration of a conventional address exclusive control system. Referring to FIG. 1, the conventional address exclusive control system comprises a first central processing unit (CPU) 1, a second CPU 2, a first input/output apparatus (IO) 3, a second IO 4, first main memory 5, second main memory 6, and a system controller (SC) 10. The system controller (SC) 10 is equipped with a new request reception function (A), an address lock judgment function (B), a request issue function (C), and a response request reception function (D).
FIG. 2 is a diagram showing a packet flow and an operation timing, both of which are for describing the operation of the conventional address exclusive control system when requesting a fetch. Referring to FIG. 2, a request for a fetch (“fetch request”) from the first CPU (CPU0) 1 is received at the SC 10 and searched for. If it is indexed that the present fetch request is for the second CPU (CPU1), the SC 10 issues a read request to the second CPU 2 which then returns, to the SC 10, a response corresponding to the read request. The SC 10 returns the returned response to the first CPU 1 as the response corresponding to the fetch request. In this case, the SC 10 carries out an address lock, thereby executing an exclusive control so as not to allow an access to the same address designation, the address lock being carried out in the midst of a search after receiving a fetch request from the first CPU 1 followed by starting a search to find what apparatus a received fetch request is for and receiving the response of a read request from the second CPU 2.
FIG. 3 is a diagram showing a packet flow and an operation timing, both of which are for describing the operation of the conventional address exclusive control system when requesting a storing. Referring to FIG. 3, a request for storing (“store request”) from the first CPU (CPU0) 1 is received at the SC 10 and searched for. If it is indexed that the present store request is to the first main memory (MEM0) 5, the SC 10 issues a store request to the first main memory 5 which then executes a memory store in response to the request and returns a response to the store request to the SC 10 upon completion of the memory store. In this case, the SC 10 carries out an address lock, thereby executing an exclusive control so as not to allow an access to the same address designation, the address lock being carried out in the midst of a search after receiving a store request from the first CPU 1 followed by starting a search to find what apparatus a received store request is for and completing a response to the store request from the first main memory 5.
FIG. 4 is a flow chart for describing the operation of the conventional address exclusive control system. Describing FIG. 4 by referring to the configuration shown in FIG. 1, the new request reception function (A) shown in FIG. 4 first receives a new request from a request source (e.g., a CPU, IO or the like) (step S1; also simply “S1” hereinafter). Then, the address lock judgment function (B) of the SC 10 searches for the address of the received request and judges whether or not an address lock is in effect, that is, whether or not the address included in the request matches the address retained in an address register (not shown in a drawing herein), thereby examining whether or not it is an “address lock match”. The process for examining the existence of the address lock match is described in detail by referring to FIG. 5.
If it is an address lock match, the access of a new request is not permitted under an exclusive control and therefore the process returns to S2 for carrying out the process therein. If it is not an address lock match, the process proceeds to S3 in which the content of the new request is set to a register. Then, the request issue function (C) of the SC 10 issues a request to the correspondent (S4). In step S5, the request issued in S4 is received by any of the CPUs 1 and 2, IOs 3 and 4, and main memories 5 and 6. Then, a response-series request related to the process is returned from any of the CPUs 1 and 2, IOs 3 and 4, and main memories 5 and 6 that have received the request so that the response request reception function (D) of the SC 10 receives the response-series request (S6). In this event, the address lock judgment function (B) of the SC 10 compares the address included in the response-series request received by the response request reception function (D) with the address existing in an address lock register (not shown in a drawing herein), thereby examining whether or not it is an address lock match (S7; refer to FIG. 5). Then, if it is an address lock match, the process proceeds to S8 in which the address lock judgment function (B) resets the lock flag of the response destination and the process ends. In contrast, if it is not an address lock match, the process proceeds to S9 in which a protocol error is detected and the process ends.
FIG. 5 is a diagram describing the operation for examining an address lock match in the conventional address exclusive control system. Describing FIG. 5 by referring to the configuration shown in FIG. 1, the address lock judgment function (B) of the SC 10 shown in FIG. 5 compares the address included in the request 8 received by the new request reception function (A) of the SC 10 with the address retained in the address lock register 7 by means of an address match discernment function 9 and, if the addresses match each other as a result of the comparison, outputs the result as an address lock match (refer to reference patent document 1). Note that the above description is provided by referring to the request 8 as a new request; the description is the same if the request 8 is a response-series request.
The conventional address exclusive control system described above is configured to determine the area of an address that is to be locked by using only the address regardless of the kind or access destination of the preceding request. The determination of the area of an address that is to be locked by using only the address has been met with the problem of also locking unnecessary access destinations. Further, the locking of even an unnecessary access destination has conventionally disabled simultaneous accesses to a plurality of addresses, consequently generating the problem of degrading the performance of the entire system.
Furthermore, if a failure (e.g., a time OUT, et cetera.) occurs due to the exclusive control of the above described address exclusive control system, there has been the problem that it is difficult to identify the suspected location of the failure because no information other than that of the locked address is left.
Further, the failure in a response request occurs after the elapse of a certain period of time after the issuance of a corresponding new request, and therefore few pieces of information related to the new request are available, thus creating the problem that it is difficult to perform an investigation including the new request.    Patent document 1: Laid-Open Japanese Patent Application Publication No. H03-196249